1. Field of the Invention
The present invention relates to a method of and a computer program product for designing patterns, and a method of manufacturing a semiconductor device. Particularly, the present invention relates to a method of and a computer program product for designing a mask pattern used in designing a circuit pattern on a substrate to be processed, and a method of manufacturing a semiconductor device using the mask pattern.
2. Description of Related Art
In recent years, along with higher integration and speeding up of semiconductor devices, requirements imposed upon a dimension of a circuit pattern have become extremely strict. Consequently, differences between a designed dimension and a finished dimension due to resolution limit in a wafer manufacturing process and the like have become obvious. As means for correcting the differences between the designed dimension and the finished dimension, various kinds of optical proximity correction (OPC) have been proposed. The OPC is a technology of correcting changes in a pattern dimension caused in a wafer manufacturing process, by partially widening a mask pattern, by providing a dummy pattern and the like fully using optical simulations.
For example, FIG. 1A shows a mask pattern 51 for forming gate wiring, the shape of a pattern end thereof is below the resolution limit and thus a pattern end of a transferred circuit pattern 52 becomes short. This is called shortening. The thinner the line width of the gate wiring becomes, the more obviously the shortening appears.
Therefore, as shown in FIG. 1B, a correction pattern 53, which is obtained by uniformly extending the mask pattern 51 in its longitudinal direction, is applied to a pattern end of the mask pattern 51. Thus, the shortening can be suppressed. Moreover, as shown in FIG. 1C, the shortening can be also suppressed by applying a hammer head 54 to a side of a pattern end of the mask pattern 51.
However, in the OPC of the related art, there is no consideration given to evenness of a base on which patterns are designed. Therefore, when patterns are designed on an uneven base, the differences between the designed dimension and the finished dimension cannot be eliminated.
For example, considered is a case where a base includes the substrate 13 to be processed and a step pattern 14 formed on the substrate 13, as shown in FIGS. 2A and 2B. In a circuit pattern 55 transferred using such a mask pattern 29 as shown in FIG. 3, which intersects with the step pattern 14, footing occurs at the intersection of the circuit pattern 55 and the step pattern 14. Therefore, a desired pattern in accordance with the mask pattern 29 cannot be designed. Thus, the footing of the circuit pattern 55 at the intersection or at the intersection and in the vicinity thereof is difficult to be corrected by the above-described OPC technology of the related art.